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FNB80460T3 motion spm? 8 series ?2017 semiconductor 1 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 april 2017 FNB80460T3 motion spm ? 8 series features ? ul certified no. e209204 (ul1557) ? 600 v - 4 a 3-phase igbt inverter including control ic for gate drive and protections ? low-loss, short-circuit rated igbts ? separate open-emitter pins from low-side igbts for three-phase current sensing ? active-high interface, works with 3.3 / 5 v logic, schmitt-trigger input ? hvic for gate driving, under-voltage and short-cir- cuit current protection ? fault output for under-voltage and short-circuit cur- rent protection ? inter-lock function to prevent short-circuit ? shut-down input ? hvic temperature-sensing built-in for temperature monitoring ? isolation rating: 1500 v rms / min. applications ? motion control - home appliance / industrial motor related resources ? an-9112 - smart power module, motion spm ? 8 series user?s guide. ? an-9548 - spm ? 8 pakage assembly guidance for 25l double dip. general description FNB80460T3 is a motion spm 8 module providing a fully-featured, high-performance inverter output stage for ac induction, bldc, and pmsm motors. these modules integrate optimized gate drive of the built-in igbts to minimize emi and losses, while also providing multiple on-module protection features including under-voltage lockouts, inter-lock function, over-current shutdown, thermal monitoring of drive ic, and fault reporting. the built-in, high-speed hvic requires only a single supply voltage and translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's robust short- circuit-rated igbts. separate negative igbt terminals are available for each phase to support the widest variety of control algorithms. package marking and ordering inform ation figure 1. 3d package drawing (click to activate 3d content) spmfa-a25 device device marking package packing type quantity FNB80460T3 nb80460t3 spmfa-a25 rail 15
FNB80460T3 motion spm? 8 series ?2017 semiconductor 2 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 integrated power functions ? 600 v - 4 a igbt inverter for three phase dc / ac power conversion ( please refer to figure 3 ) integrated drive, protectio n and system control functions ? for inverter high-side igbts: gate drive circ uit, high-voltage isolated high-speed level shifting control circuit under-voltage lock-out (uvlo) protection note: available bootstrap circuit ex ample is given in figures 5 and 17 ? control circuit under-voltage lock-out (uvlo) protection ? for inverter low-side igbts: gate drive circuit, over curent pretection(ocp), s hort-circuit protection (scp) control supply circuit under-vol tage lock-out (uvlo) protection ? fault signaling: corresponding to uvlo (low-side supply) and sc faults ? input interface: high-active interface, wor ks with 3.3 / 5 v logic, schmitt trigger input pin configuration figure 2. top view (1) p (2) u, vs u (3) n u (4) v, vs v (5) n v (6) w, vs w (7) n w (8) com (9) /fo,/sd w ,v ts (10) csc (11) v dd (12) in wl (13) in wh (14) vb w (15) /sd v (16) v dd (17) in vl (18) in vh (19) vb v (20) /sd u (21) v dd (22) in ul (23) in uh (24) com (25) vb u case temperature (tc) detecting point
FNB80460T3 motion spm? 8 series ?2017 semiconductor 3 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 pin descriptions pin number pin name pin description 1 p positive dc-link input 2u, vs u output for u phase 3n u negative dc-link input for u phase 4v, vs v output for v phase 5n v negative dc-link input for v phase 6w, vs w output for w phase 7n w negative dc-link input for w phase 8 com common supply ground 9 /fo, /sd w , v ts fault output, shut-down input for w phase, temperature output of drive ic 10 c sc shut down input for over current and short circuit protection 11 v dd common bias voltage for ic and igbts driving 12 in wl signal input for low-side w phase 13 in wh signal input for high-side w phase 14 vb w high-side bias voltage for w-phase igbt driving 15 /sd v shut-down input for v phase 16 v dd common bias voltage for ic and igbts driving 17 in vl signal input for low-side v phase 18 in vh signal input for high-side v phase 19 vb v high-side bias voltage for v-phase igbt driving 20 /sd u shut-down input for u phase 21 v dd common bias voltage for ic and igbts driving 22 in ul signal input for low-side u phase 23 in uh signal input for high-side u phase 24 com common supply ground 25 vb u high-side bias voltage for u-phase igbt driving
FNB80460T3 motion spm? 8 series ?2017 semiconductor 4 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 internal equivalent circ uit and input/output pins figure 3. internal block diagram note: 1. inverter high-side is composed of three igbts, freewheeling diodes. 2. inverter low-side is composed of three igbts, freewheeling diodes. 3. inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals. vb ho hin lo vs lin csc /fo, /sd w , v ts com v dd csc /fo, /sd w , v ts in wh vb w nw nv n u w,vs w v,vs v u,vs u p ho lo vs ho lo vs com v dd in wl vb hin lin v dd /sd v in vh vb v v dd in vl /sd v vb hin lin v dd /sd u in uh vb u v dd in ul /sd u com com com
FNB80460T3 motion spm? 8 series ?2017 semiconductor 5 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 absolute maximum ratings (t j = 25c, unless otherwise specified.) inverter part control part total system thermal resistance note: 4. these values had been made an acquisition by the calculation considered to design factor. 5. for the measurement point of case temperature (t c ), please refer to figure 2. symbol parameter conditions rating unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces collector - emitter voltage 600 v i c each igbt collector current t c = 25c, t j 150c (note 4) 4 a i cp each igbt collector current (peak) t c = 25c, t j 150c, under 1 ms pulse width (note 4) 8a t j operating junction temperature -40 ~ 150 c symbol parameter conditions rating unit v dd control supply voltage applied between v dd - com 20 v v bs high-side control bias voltage applied between vb u - vs u , vb v - vs v , vb w - vs w 20 v v in input signal voltage applied between in uh , in vh , in wh , in ul , in vl , in wl - com -0.3 ~ v dd +0.3 v v fs function supply voltage applied between /fo, /sd w ,v ts - com -0.3 ~ v dd +0.3 v i fo fault current sink current at /fo, /sd w ,v ts pin 2 ma v sc current sensing input voltage applied between c sc - com -0.3 ~ v dd +0.3 v symbol parameter conditions rating unit v pn(prot) self protection supply voltage limit (short circuit protection capability) v dd = v bs = 13.5 ~ 16.5 v, t j = 150c, non-repetitive, < 2 ? s 400 v t stg storage temperature -40 ~ 125 c v iso isolation voltage connect pins to heat sink plate ac 60 hz, sinusoidal, 1 minute, connection pins to heat sink plate 1500 v rms symbol parameter conditions min. typ. max. unit r th(j-c)q junction to case thermal resistance (note 5) inverter igbt part, (per module) - - 3.65 c / w r th(j-c)f inverter fwdi part, (per module) - - 4.13 c / w
FNB80460T3 motion spm? 8 series ?2017 semiconductor 6 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 electrical characteristics (t j = 25c, unless otherwise specified.) inverter part note: 6. t on and t off include the propagation delay of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under the given gate driving condition internally. for the detailed information, please see figure 4. figure 4. switching time symbol parameter conditions min. typ. max. unit v ce(sat) collector - emitter saturation voltage v dd = v bs = 15 v v in = 5 v i c = 3 a t j = 25c - 1.85 2.30 v t j = 150c - 2.30 - v v f fwdi forward voltage v in = 0 v i f = 3 a t j = 25c - 1.95 2.50 v t j = 150c - 1.85 - v hs t on switching times v pn = 400 v, v dd = v bs = 15 v, i c = 4a t j = 25c v in = 0 v ? 5 v, inductive load (note 6) 0.30 0.70 1.10 us t c(on) -0.150.45us t off -0.501.00us t c(off) -0.100.40us t rr -0.10- us ls t on v pn = 400 v, v dd = v bs = 15 v, i c = 4a t j = 25c v in = 0 v ? 5 v, inductive load (note 6) 0.30 0.70 1.10 us t c(on) -0.150.45us t off -0.501.00us t c(off) -0.100.40us t rr -0.10- us i ces collector - emitter leakage current v ce = v ces - - 1.00 ma hinx linx i cx v cex 10% i cx 10% v cex 10% i cx 90% i cx t off t on t c(off) t c(on) 10% v cex t rr 100% i cx
FNB80460T3 motion spm? 8 series ?2017 semiconductor 7 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 figure 5. example circuit for switching test figure 6. switching loss characteristics figure 7. v-t curve of temperature output of ic one-leg diagram of spm 8 p n u,v,w i c v pn u,v,w inductor hs switching ls switching v 400v v v +15v +5v 10k ? c bs hs switching ls switching v in 0v 5v v dd vb ho hin lo vs lin csc /fo, /sdw, v ts com v dd +15v v bs v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 switching loss e sw [uj] collector current, i c [amperes] igbt turn-on, eon igbt turn-off, eoff frd turn-off, erec inductive load, v pn = 300v, v dd =15v, t j =25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 50 100 150 200 inductive load, v pn = 300v, v dd =15v, t j =150 switching loss e sw [uj] collector current, i c [amperes] igbt turn-on, eon igbt turn-off, eoff frd turn-off, erec 0 25 50 75 100 125 150 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 v ts from pin 9 [v] t hvic [ o c] 3.3v pull-up with 4.7kohm 5v pull-up with 10kohm
FNB80460T3 motion spm? 8 series ?2017 semiconductor 8 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 control part note: 7. short-circuit current protection functi on is for all six igbts if the /fo, /sd w , v ts pin is connected to /sd x pins. symbol parameter conditions min. typ. max. unit i qdd quiescent v dd supply current v dd = 15 v, in (uh,vh,wh,ul,vl,wl) = 0 v v dd - com - - 1.7 ma i pdd operating v dd supply current v dd = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input v dd - com - - 1.8 ma i qbs quiescent v bs supply current v bs = 15 v, in (uh, vh, wh) = 0 v v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) - - 100 ? a i pbs operating v bs supply current v dd = v bs = 15 v, f pwm = 20 khz, duty = 50%, applied to one pwm signal input for high - side v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) - - 300 ? a v foh fault output voltage v sc = 0 v, v f circuit: 10 k ? to 5 v pull-up 3.81 - - v v fol v sc = 1 v, v f circuit: 10 k ? to 5 v pull-up - - 0.5 v v sc(ref) short-circuit trip level v dd = 15 v (note 7) 0.46 0.49 0.52 v uv ddd supply circuit under-voltage protection detection level 10.0 11.5 13.0 v uv ddr reset level 10.5 12.0 13.5 v uv bsd detection level 9.5 11.0 12.5 v uv bsr reset level 10.0 11.5 13.0 v i fo_t hvic temperature sensing current v dd = v bs = 15 v, t hvic = 25c - 82.5 - ? a v dd = v bs = 15 v, t hvic = 75c - 207.5 - ? a v fo_t hvic temperature sensing voltage see figure 7 v dd = v bs = 15 v, t hvic = 25c, 10 k ? to 5 v pull-up - 4.18 - v v dd = v bs = 15 v, t hvic = 75c, 10 k ? to 5 v pull-up - 2.93 - v t fod fault-out pulse width 40 - - ? s v fsdr shut-down reset level applied between /fo - com - - 2.4 v v fsdd shut-down detection level 0.8 - - v v in(on) on threshold voltage applied between in (uh) , in (vh) , in (wh) , in (ul) , in (vl) , in (wl) - com --2.4v v in(off) off threshold voltage 0.8 - - v
FNB80460T3 motion spm? 8 series ?2017 semiconductor 9 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 bootstrap diode part figure 8. built-in bootstrap diode charaterstics recommended oper ating conditions note: 8. this product might not make response if input pulse width is less than the recommanded value. symbol parameter conditions min. typ. max. unit r bs bootstrap diode resitance v dd = 15v, t j = 25c - 280 - ? symbol parameter conditions min. typ. max. unit v pn supply voltage applied between p - n u , n v , n w - 300 400 v v dd control supply voltage applied between v dd - com 14.0 15 16.5 v v bs high - side bias voltage applied between vb u - vs u , vb v -vs v , vb w - vs w 13.0 15 18.5 v dv dd / dt, dv bs / dt control supply variation -1 - 1 v / ? s t dead blanking time for preventing arm - short for each input signal 0.5 - - ? s v sen voltage for current sensing applied between n u , n v , n w - com (including surge voltage) -4 4 v p win(on) minimun input pulse width v dd = v bs = 15 v, i c ?? 10 a, wiring inductance between n u, v, w and dc link n < 10nh (note 8) 0.7 - - ? s p win(off) 0.7 - - 0123456789101112131415 0.00 0.01 0.02 0.03 0.04 0.05 0.06 i f [a] v f [v] t j =25 o c, v dd =15v
FNB80460T3 motion spm? 8 series ?2017 semiconductor 10 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 mechanical characteristics and ratings figure 9. flatness measurement position figure 10. mounting screws torque order note: 9. do not make over torque when mounting screws. much mounting torque may cause package cracks, as well as bolts and al heat-si nk destruction. 10. avoid one side tightening stress. figure 10 shows the recommended torque order for mounting screws. uneven mounting can cause of package to be damaged. the pre-screwing torque is set to 20 ~ 30 % of maximum torque rating. parameter conditions min. typ. max. unit device flatness see figure 9 -50 - 100 ? m mounting torque mounting screw: - m3 see figure 10 recommended 0.7 n ? m 0.6 0.7 0.8 n ? m recommended 7.1 kg ? cm 5.9 6.9 7.9 kg ? cm weight -5.0- g pre ? screwing : 1 ? 2 final screwing : 2 ? 1 1 2
FNB80460T3 motion spm? 8 series ?2017 semiconductor 11 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 time charts of protective function figure 11. under-voltage protection (low-side) a1 : control supply voltage rises: after the voltage rises uv ddr , the circuits start to operate when next input is applied. a2 : normal operation: igbt on and carrying current. a3 : under voltage detection (uv ddd ). a4 : igbt off in spite of control input condition. a5 : fault output operation starts. a6 : under voltage reset (uv ddr ). a7 : normal operation: igbt on and carrying current. figure 12. under-voltage protection (high-side) b1 : control supply voltage rises: after the voltage reaches uv bsr , the circuits start to operate when next input is applied. b2 : normal operation: igbt on and carrying current. b3 : under voltage detection (uv bsd ). b4 : igbt off in spite of control input c ondition, but there is no fault output signal. b5 : under voltage reset (uv bsr ) b6 : normal operation: igbt on and carrying current input signal output current fault output signal control supply voltage reset uv ddr protection circuit state set reset uv ddd a1 a3 a2 a4 a6 a5 a7 input signal output current fault output signal control supply voltage reset uv bsr protection circuit state set reset uv bsd b1 b3 b2 b4 b6 b5 high-level (no fault output)
FNB80460T3 motion spm? 8 series ?2017 semiconductor 12 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 figure 13. inter-lock function d1 : high side first - input - first - output mode d2 : low side noise mode : no lo d3 : high side noise mode : no ho d4 : low side first - input - first - output mode d5 : in - phase mode : no ho figure 14. fault-out function by over current protection hin : high-side input signal lin : low-side input signal ho : high-side output signal lo : low-side output signal c sc : over current detection input /fo : fault out function hi n lin ho lo /fo hin : high-side input signal lin : low-side input signal ho : high-side igbt gate vol tage lo : low-side igbt gate voltage /fo : fault output d1 d2 d3 d4 d5 hin lin ho lo csc /fo no output activated by next input after fault clear over-current detection soft off smart turn-off
FNB80460T3 motion spm? 8 series ?2017 semiconductor 13 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 figure 15. shutdown input function by external command hin : high-side input signal lin : low-side input signal ho : high-side output signal lo : low-side output signal c sc : over current detection input /sd x : shutdown input function input/output interface circuit figure 16. recommended mcu i/o interface circuit note: 11. rc coupling at each input (parts shown dotted) might change depending on the pwm control scheme used in the application and the wiring impedance of the application?s printed circuit board. the input signal section of the spm 8 product integrates 5 k ?? ( typ.) pull-down resistor. therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal. hin lin ho lo c sc /sd x no output activated by next input after fault clear external shutdown input soft off smart turn-off mcu com 5 v line (mcu or control power) /fo , /sd w , v ts r pf = 10k ? spm in uh , in vh , in wh in ul , in vl , in wl
FNB80460T3 motion spm? 8 series ?2017 semiconductor 14 www.fairchildsemi.com www.onsemi.com FNB80460T3 rev. 1.0 figure 17. typical application circuit note: 12. to avoid malfunction, the wiring of each input should be as short as possible. (less than 2 ~ 3 cm) 13. /fo is open-drain type. this signal line should be pulled up to the positive side of the mcu or control power supply with a resistor that makes i fo up to 2 ma. please refer to figure 16. 14. c sp15 of around seven times larger than bootstrap capacitor c bs is recommended. 15. input signal is active-high type. there is a 5 k ? resistor inside the ic to pull down each input signal line to gnd. rc coupling circuits is recommanded for the prevention of input signal oscillation. r s c ps time constant should be selected in the range 50 ~ 150 ns . ( recommended r s = 100 ? , c ps = 1 nf) 16. each wiring pattern inductance of a point should be minimized (recommend less than 10nh). use the shunt resistor r s(u/v/w) of surface mounted (smd) type to reduce wir- ing inductance. to prevent malfunction, wiring of point e sh ould be connected to the terminal of the shunt resistor r s(u/v/w) as close as possible. 17. to prevent errors of the protection function, the wiri ng of b, c, and d point should be as short as possible. 18. in the short-circuit protection circuit, please select the r f c sc time constant in the range 1.5 ~ 2 ? s. do enough evaluation on the real system because short-circuit protection time may very wiring pattem layout and value of the r f and c sc time constant. 19. the connection between control gnd line and power gnd line which includes the n u , n v , n w must be connected to only one point. please do not connect the control gnd to the power gnd by the broad pattern. also, the wiring distance between control gnd and power gnd should be as short as possible. 20. each capacitor should be mounted as close to the pins of the motion spm 8 product as possible. 21. to prevent surge destruction, the wiring between the smoothing capacitor and the p and gnd pins should be as short as possi ble. the use of a high frequency non-inductive capacitor of around 0.1 ~ 0.22 ? f between the p and gnd pins is recommended. 22. relays are used at almost every systems of electrical equipment s of home appliances. in these cases, there should be suffi cient distance between the cpu and the relays. 23. the zener diode or transient voltage suppressor should be adopted for the protection of ics from the surge destruction betw een each pair of control supply terminals. (recommanded zener diode is 22 v / 1 w, which has the lower zener impedance characteristic than about 15 ? ) 24. please choose the electrolytic capacitor with good temperature characteristic in c bs . also, choose 0.1 ~ 0.2 ? f r-category ceramic capacitors with good temperature and frequency characteristics in c bsc . 25. for the detailed information, please refer to the application notes. 26. /fo and /sd must be connected as short as possible. vb ho hin lo vs lin csc /fo, /sdw, v ts com v dd csc /fo, /sdw, v ts in wh vb w nw nv nu w,vs w v,vs v u,vs u p ho lo vs ho lo vs com v dd in wl vb hin lin v dd /sd v in vh vb v v dd in vl /sd v vb hin lin v dd /sd u in uh vb u v dd in ul /sd u com com c bs c bsc c bs c bsc c bs c bsc a e m v dc c dcs r sw r sv r su w-phase current v-phase current u-phase current 15v c sp15 c spc15 com r f input signal for short-circuit protection c sc fault gating wl gating wh gating vl gating vh gating ul gating uh m c u r s c ps r s c ps r s c ps r s c ps r s c ps r s c ps c pf 5v b d c power gnd line control gnd line
notes: unless otherwise specified a) no packaging standard applies b) all dimensions are in millimeters c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions d) ( ) is reference e) drawing filename: mod25darev2 (1.70) 22x1.30=28.60 ? (1.70) 0.50 ? 18x max 0.80 14.30 ? 14.30 ? 1 7 8 25 13.00 ? 14.30 ? (1.70) (3.00) 32.00 ? 14.00 ? 1.30 ? 2.60 ? 3.90 ? 7x max 1.00 0.60 ? 7x (0.45) 2.90 ? (0.70) (0.55) 0.40 +0.10 -0.05 (r0.50) 18.00 ? ? 20.70 ? (9.50) (11.44) (9.00) (11.70) 1.30 ? 12x 2.60 ? 5x (0.45) > 3.20 ? 2x
www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? semiconductor components industries, llc

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